JEDEC has officially released DDR5 SDRAM standards
The industry-standard organization JEDEC, which is developing standards for the microelectronic industry, has approved the final specification of DDR5 RAM (Double Data Rate 5). The new standard for DRAM, widely used in consumer electronics, has received the internal designation JESD79-5 .
Recall that, JEDEC announced DDR5 back in 2017 . That is, the development of a new standard took three years. However, even before the adoption of the standard, the leading DRAM manufacturers – Samsung, SK Hynix and Micron – had working samples of DDR5 modules on 16 Gbit chipset. Now the companies will start production and start delivering DDR5 DIMM modules for servers this year. By the way, at the same time JEDEC announced the adoption of the standard, Micron announced the launch of the Technology Enablement Program, aimed at accelerating the adoption of DDR5 memory and the release of related devices using it. The main players in the market have already joined the initiative: Cadence, Montage, Rambus, Renesas and Synopsys.
The DDR5 specification provides increased performance up to 6400 MT / s (millions of transactions per second) from 3200 MT / s for previous generation memory while reducing voltage from 1.2 to 1.1 V, which will provide a significant increase in energy efficiency (GB / s per watt power consumption) compared with previous generation memory.
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It is important to stipulate that at first, lower-speed DDR5-4800 modules will be available (current DDR4 DIMMs support frequencies of 2800-3200 MHz), and faster overclocking models will appear only with time.
However, the main advantage of DDR5 is not speed, but volume. The minimum density of a single DDR5 chip is 8 Gb, and the maximum is 64 Gb (4X8 GB), which is four times higher than the DDR4. This will allow the creation of 128 GB UDIMMs, and with server-side LRDIMMs, the maximum capacity will reach an impressive 2 TB.
The number of banks in comparison with DDR4 has doubled – from 16 in 4 groups to 32 in 8 groups, as well as the maximum packet length (the amount of data transmitted by one read or write command) – from 8 to 16.
The number of pads has not changed – there are still 288 of them, but the keys will be located differently, which will exclude the possibility of installing the DDR5 module in the wrong slot.
It is known that AMD EPYC Genoa (Zen 4) and Intel Xeon Scalable Sapphire Rapids server processors will support DDR5 DRAM. As for the appearance of DDR5 in mass PCs, this should not be expected before the second half of 2021, or even the beginning of 2022. According to IDC’s forecast, next year DDR5 memory will occupy 22% of the total DRAM market, and by the end of 2022 its share will reach 43% of the total. By the way, DDR4 crossed the 45 percent milestone in 2016.